A High-PSR EMI-Resistant NMOS-Only Voltage Reference Using Zero- $V_T$ Active Loads

Abstract

Electromagnetic interference (EMI) disturbances coupled in the power supply of voltage and current references can severely degrade their performance, due to its finite power supply rejection (PSR). The design of a 90-dB PSR 4-dBm EMI-resistant NMOS-only voltage reference is herein presented. The voltage reference is designed based on the zero-temperature-coefficient transistor operating point. The high PSR is obtained using zero- $V_{T}$ transistors as active loads in the open and feedback loop of the circuit. Two versions, using standard $V_{T}$ and low-power $V_{T}$ transistors, were designed in a 130-nm CMOS process. Both are designed using the same thermal compensation principle. The circuits occupy 0.014 and 0.006 mm $^{2}$ of silicon area while consuming around 1.15 and 0.156 $\mu$ W at 27 $^\circ$ C, respectively. Postlayout simulations present a reference voltage of 206 and 450 mV with an average temperature coefficient of 321 and 86 ppm/ $^\circ$ C (1000 samples), under a temperature range from $-$ 55 to 125 $^\circ$ C. An EMI source of 4 dBm (1 $\text{V}_{\text{pp}}$ ) injected in the power supply, according to the direct power injection standard, yields $-$ 0.17% and $-$ 0.1 ${\%}$ of the maximum dc shift and 822 and 950 $\mu \text{V}_{\text{pp}}$ of the maximum peak-to-peak ripple for the standard $V_{T}$ and low-power $V_{T}$ implementations, respectively.