A High Power Supply Rejection and Fast Settling Time Capacitor-Less LDO

Abstract

This paper presents an internally compensated capacitor-less low dropout regulator (CL-LDO) with bulk-driven feed-forward supply noise cancellation and adaptive compensation for fast settling time (TS ). A feed-forward path from the CL-LDO's supply input to the output is implemented to increase power supply rejection (PSR) from mid-range frequencies to up to 5 MHz. The CL-LDO achieves a -90 dB low frequency and -64 dB PSR at 1 MHz for 50 mA of load current (IL). A transconductance amplifier with adaptive Miller compensation based on IL sense is used to increase the unity-gain frequency by 40× at heavy loads. The CL-LDO achieves a 0.3 mV/V line regulation, 10 μV/mA load regulation, 300 ns of TS, and 0.16 ps figure of merit, which is 7.5× better than current state-of-the-art CL-LDOs. The CL-LDO was fabricated in CMOS 130 nm technology, consumes IQ of 42 μA, has a dropout voltage (VDO) of 200 mV for IL of 50 mA, and occupies an active area of 0.0046 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .