Abstract
Future generations of microprocessors are expected to exhibit much heavier loads and much faster transient slew rates. Today's voltage regulator module (VRM) will need a large amount of extra decoupling and output filter capacitors to meet future requirements, which basically makes the existing VRM topologies impractical. As a candidate topology, the interleaved quasi-square-wave (QSW) exhibits very good performance, such as fast transient response and very high power density. The limitation in the application of the interleaved parallel technology is current sharing control. In this paper, a novel current sensing and current sharing technique is proposed. With this technique, current sharing can be controlled simply in parallel converters without current transformer and current sensing resistors. Experimental results verify that with this technique, a 4-module interleaved QSW VRM has high power density, high efficiency and fast transient response.
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