A high performance/low power 16 K-byte 4-way set associative integrated cache macro

Abstract

The high-performance, low-power 16 K-byte 4-way set associative integrated cache memory currently being used in the IBM 486 SLC/486 SLC2 microprocessor chips is described. The integrated cache combines the functions of the 20 K bit TAG memory, 1 K bit STATE, 2 K bit LRU (least recently used), and 144 K bit DATA memory. This is key to reducing interface complexity and optimizing size, power, and performance. The integrated cache unit has a typical clock to DATA access of 6.9 ns and clock to HIT access of 5.0 ns in a 12 ns cycle time. It has a worst-case power of 400 mW at 50% utilization. The integrated cache was designed and built in 0.8 /spl mu/m CMOS technology. It features novel circuit design techniques such as high-performance dynamic comparators in TAG and LRU arrays, self-timed restore, read-modified-write on all arrays in one cycle, and very fast flush/reset in STATE array.