Abstract
This paper presents a high performance real-time simulator for power electronic systems applications and primarily intended for controller hardware-in-the-loop (CHIL) testing. The novelty of the proposed simulator resides in the massively parallel hardware architecture that efficiently exploits fine-grained parallelism without imposing severe communication overhead time that can limit the performance. The simulator enables the use of a nanosecond range simulation timestep to simulate power electronic systems. Through the use of this nanosecond range simulation timestep, the simulator minimizes the error arising from the intersimulation timestep switching phenomenon associated with CHIL. The proposed hardware architecture is realized based on the FPGA technology. The simulator is tested and its CHIL capability verified based on the closed-loop testing of a robust multivariable servomechanism controller for autonomous operation of a distributed generation unit.
Highlights
Microgrids and smart grids are the new concepts which have been brought about due to high penetration of renewable energy systems, distributed generation (DG) units, and storage systems
In the grid-connected mode, a microgrid including its loads and DG units is connected to the main grid at the point of common coupling (PCC)
This paper presents a high-performance real-time simulator for controller hardware-in-the-loop
Summary
Microgrids and smart grids are the new concepts which have been brought about due to high penetration of renewable energy systems, distributed generation (DG) units, and storage systems. Arrangement of a physical controller platform, in association with a real-time simulator, is needed to safely and thoroughly verify the design integrity and evaluate its functions and performance [1,2,3,4] This type of HIL testing, involving the exchange of waveforms between the simulator and the controller platform at the signal level with no real power exchange, is called controller hardware-in-the-loop (CHIL) testing. This parallel hardware architecture efficiently exploits fine-grained parallelism without imposing sever communication and synchronization overhead times that can limit the performance This simulator provides the inherent capability to relax the accuracy and bandwidth limits of the existing real-time simulators.
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