A high performance alternating projections image demosaicing hardware

Abstract

Since capturing three color channels (red, green, and blue) per pixel increases the cost of digital cameras, most digital cameras capture only one color channel per pixel using a single image sensor. The images pass through a color filter array before being captured by the image sensor. Demosaicing is the process of reconstructing the missing color channels of the pixels in the color filtered image using their available neighboring pixels. Alternating Projections (AP) is one of the highest quality image demosaicing algorithms, and it has very high computational complexity. Therefore, in this paper, a high performance AP image demosaicing hardware is proposed. This is the first AP image demosaicing hardware in the literature. The proposed hardware is implemented using Verilog HDL. The Verilog RTL code is verified to work correctly in a Xilinx Virtex 6 FPGA. The FPGA implementation can process 31 full HD (1920×1080) images per second.