Abstract
Multi-processor system-on-chip (MPSoC) is an integrated circuit containing multiple cores that implements most of the functionality of a complex electronic system and some other components like FPGA/ASIC on single chip. The most crucial things in such like these systems are the performance, energy, power and area optimization. Moreover, scheduling the tasks of an application on to the processors (cores) and HW/SW partitioning are inter-dependent in the traditional design space exploration process. In this paper, we propose an algorithm to produce the optimality of scheduling and optimize the number of cores that can be used and also reduce the overall execution time and number of buses on the chip by using efficient hardware-software co-design partitioning technique. The viability and potential of the proposed algorithm is demonstrated by extensive experimental results to conclude that the proposed algorithm is an efficient scheme to obtain the optimality of scheduling and partitioning with hard and large task graph problems.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.