Abstract
In this paper, a high linearity PWCL is proposed. By using the linear control stage and digital-controlled charge pump (DCCP), the proposed PWCL can be operated in wide range of input duty cycle and produced wide range of output duty cycle in wide frequency range. Utilizing simple detect circuit to control DCCP in complementary architecture, the proposed PWCL can reduce lock time ratio to 4.9. The test chip was fabricated in 0.18?m CMOS process. The measurement results show that the frequency range of input signal is from 50MHz to 1.3GHz, the duty cycle range of input signal is from 30% to 70% and the programmable duty cycle of output signal is from 30% to 70% in steps of 5%. The measurement power dissipation and the peak-to-peak jitter are 4.8mW and 13.2ps respectively at an operation frequency of 1.3GHz.
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