Abstract

This letter presents a 7–9-GHz four-element eight-beam receiver front end (FE) in 65-nm CMOS for satellite communications. To boost the linearity and defeat interferences, the FE proposes a strength-oriented nonlinearity cancellation (SoNC) technique based on multigate transistors (MGTRs). It demonstrates a 22-dB single-element gain with a 7-dB noise figure (NF) at 7.5 GHz. The measured input-referred 1-dB gain compression point (IP <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{1\, dB}})$</tex-math> </inline-formula> and third-order input interception point (IIP <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{3})$</tex-math> </inline-formula> at 7.5 GHz are <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 12 and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 7.5 dBm, respectively. The chip occupies 19.8 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> and consumes 1265 mW, and achieves an excellent linearity among silicon-based RF-beamforming receivers.

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