A High-Level Synthesis Implementation and Evaluation of an Image Processing Accelerator

Dimitris Tsiktsiris,Dimitris Ziouzios,Minas Dasygenis

doi:10.3390/technologies7010004

Dimitris Tsiktsiris, Dimitris Ziouzios + Show 1 more

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https://doi.org/10.3390/technologies7010004

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Journal: Technologies	Publication Date: Dec 23, 2018
Citations: 9	License type: CC BY 4.0

Affiliation: University of Western Macedonia

Abstract

Most frequently, an FPGA is used as an implementation platform in applications of graphics processing, as its structure can effectively exploit both spatial and temporal parallelism. Such parallelization techniques involve fundamental restrictions, namely being their dependence on both the processing model and the system’s hardware constraints, that can force the designer to restructure the architecture and the implementation. Predesigned accelerators can significantly assist the designer to solve this problem and meet his deadlines. In this paper, we present our accelerators for Grayscale and Sobel Edge Detection, two of the most fundamental algorithms used in digital image processing projects. We have implemented those algorithms with a “bare-metal” VHDL design, written purely by hand, as a portable USB accelerator device, as well as an HLS-based overlay of a similar implementation designed to be used by a Python interface. The comparisons of the two architectures showcase that the HLS generated design can perform equally to or even better than the handwritten HDL equivalent, especially when the correct compiler directives are provided.

Highlights

Speaking, real-time image processing on a serial processor is very difficult to achieve, mainly due to the large dataset represented by the image or the complex operations that may need to be performed [1]
We do the same for the new High-Level Synthesis (HLS) implementation and, we present the results of our work
For the field-programmable gate array (FPGA) design community, it appears that HLS technology is transitioning from research and investigation to selected deployment [26]

Summary

Introduction

Real-time image processing on a serial processor is very difficult to achieve, mainly due to the large dataset represented by the image or the complex operations that may need to be performed [1]. FPGAs have become popular as implementation platforms, mainly due to their continual growth in functionality and size, especially for image processing applications and video processing [3]. A first step for many digital image processing applications and computer vision is the edge detection. Edge detection in general can reduce significantly the amount of data in an image, while the structural properties of the image are preserved, in order to be used for further image processing [4], reducing the processing complexity and facilitating the implementation of the main algorithm [5]. Edge detection is a valuable step in image processing, it is very taxing in hardware and power requirements; the need for a dedicated accelerator is inevitable.

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