A High Energy Efficiency and Low Resource Consumption FPGA Accelerator for Convolutional Neural Network

Abstract

With the rapid development of convolutional neural networks (CNN), the design of hardware accelerators for CNN calculations has become a major focus of current research. However, power consumption and resource consumption are two main limits for the application of CNN hardware accelerators. In response to these problems, a FPGA-based implementation of a CNN hardware accelerator with high energy efficiency and low resource consumption is proposed. The implementation includes zero padding, convolution, batch normalization, ReLU6, and MaxPooling. The computing performance of the network is improved by using pipeline design and layer fusion. The LeNet-5 network is to test the implementation on the Xilinx Virtex VC-707 FPGA board. The experimental result shows that when inferring the MNIST test set, the energy efficiency is 843.91 times and 228.35 times that of the CPU and GPU, respectively.