Abstract

This paper describes the design and measured performance of a high-efficiency and linearity-enhanced K-band MMIC amplifier fabricated with a 0.15 μm GaAs pHEMT processing technology. The linearization enhancement method utilizing a parallel nonlinear capacitance compensation diode was analyzed and verified. The three-stage MMIC operating at 20–22 GHz obtained an improved third-order intermodulation ratio (IM3) of 20 dBc at a 27 dBm per carrier output power while demonstrating higher than a 27 dB small signal gain and 1-dB compression point output power of 30 dBm with 33% power added efficiency (PAE). The chip dimension was 2.00 mm × 1.40 mm.

Highlights

  • GaAs MMIC is regarded as the premier power device for the microwave communication system [1] and phase array radar system [2] witnessed in recent decades

  • This paper presents a high-efficiency K-band MMIC linear power amplifier fabricated with a 0.15 μm GaAs pHEMT processing technology

  • The K-band MMIC linear amplifier is composed of three-stage FETs fabricated with a 0.15 μm gate length AlGaAs/GaAs pHEMT technology

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Summary

Introduction

GaAs MMIC is regarded as the premier power device for the microwave communication system [1] and phase array radar system [2] witnessed in recent decades. When facing high peak-to-average ratio (PAR) modulation schemes such as QPSK and OFDM, the nonlinearity of the power amplifier causes spectral reproduction and intermodulation distortion. To meet the linearity requirements in the point-to-point radio or satellite communications which usually operate with a high PAR and inconstant enveloped input signal, conventional designs have to work at a back-off output point compared to their saturated power level. Several techniques have been employed to improve the efficiency in the low power region, such as the linear Doherty design, feed-forward technique, and envelop feedback. Some linear Doherty amplifier [4] and feed-forward designs [5] show a high linearity at an acceptable efficiency; the complexity and cost of chips are not low. Class-J [6] was reported to achieve a high linearity in the back-off region

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