A high-density and low-power charge-based Hamming network

Abstract

A charge-based programmable Hamming neural network circuit is proposed. It utilizes capacitive comparators as processing elements in the feedforward layer, and a multiport charge-sensing amplifier as the MAXNET (or winner-take-all (WTA)) circuit. The CMOS prototype chip contains 10*10 fully interconnected processing elements with the capability of encoding 10 exemplar patterns. The whole circuit occupies a silicon area of 0.414 mm/sup 2/ fabricated in a 2- mu m CMOS technology. The low-silicon area and low-power dissipation are the fundamental properties of the proposed implementation. The experimental results from a prototype chip show robust retrieval and excellent classification properties as theoretically predicted. A modularity methodology and how to extend the prototype chip to VLSI system level integration are examined.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>