Abstract
Reconfigurable computing is being widely used in Computation-intensive applications. With the rapid development of applications, we have higher requirements for the computational efficiency of reconfigurable computing. In order to improve the computational efficiency, the array size gradually increased for applications that are more complex. With the upgrade of the array size, the hardware overhead of traditional interconnection structure used for reconfigurable processing unit (RPU) increases significantly. This paper proposed a new interconnection structure called hierarchical local interconnection for RPU. Comparing to traditional full-mesh structure used in MorphoSys, the hierarchical local interconnection greatly enhanced the area efficiency while retaining the flexibility of interconnection. When the array scale is 8 × 8, hardware overhead of new structure is 28.6 % of the traditional structure.
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