A heuristic method for obstacle avoiding group Steiner tree construction

Abstract

Very large scale integration (VLSI) global routing is typically performed on a rectangular die space amidst multiple IP cores and gates, typically treated as obstacles during net routing. In this paper, we address the global routing problem of a multi-terminal net in presence of obstacles, and name it as Obstacle-avoiding Group Steiner tree (OAGST) construction. The proposed method comprises of the following procedures. Given a number of obstacles, and pins (terminals) on a die, (1) first empty rectangular regions, called maximal empty rectangles, are constructed avoiding obstacles. (2) Next, a split - and - merge technique is adopted to regenerate L-shaped rectilinear regions over the maximal empty rectangles. Partial Rectilinear Steiner tree (RST) is constructed from each L-shaped region by routing the pin terminals inside the region. (3)The split - and - merged regions are next converted to a dual graph following neighbouring corner-stich method. Finally, a complete Obstacle-avoiding Group Steiner tree/Rectilinear Steiner tree is constructed from the dual graph by redundant edge deletion. A comparative study of our algorithm with an existing work shows improvement in many cases.