A heuristic approach to achieving a BIT False Alarm Rate

Abstract

High Built-In-Test (BIT) False Alarm Rates (FAR) lead to loss of confidence in the product's embedded tests system due to high re-work costs. This paper defines a heuristic BIT development methodology for achieving a desired FAR. Purely statistical approaches to achieving a desired FAR do not take into account real world contributors to high FARs. To ensure an ability to measure FAR, the BIT design considerations listed below need to be taken into account: a) BIT construction, b) test limit derivation based on expected design performance, c) BIT data collection through return of parametric measurement data, d) ability to correlate collected parametric data across various test environments, and e) use of statistical analysis tools to establish model performance over environments. Using these techniques allows design of an embedded test system whose performance can be analytically established, verified through actual collection of parametric data, and validated through analytical modeling techniques; allowing the BIT developer to implement Corrective Action (CA) required to achieve the desired FAR.