A heterogeneous SoC architecture with embedded virtual FPGA cores and runtime Core Fusion

Abstract

Hardware virtualization is a well known technique in processor based hardware architectures for abstraction of the complexity of an underlying hardware from the programmer. Not only processor based hardware, especially Field Programmable Gate Arrays (FPGA), comes with a high complexity and the exploitation for developers suffer from this fact. Each change in the hardware e.g. through an introduction of a new series results in a re-design of the applications. Therefore, a novel concept for FPGA hardware virtualization is introduced in this paper. The advantage with this approach is that the specification of the virtual FPGA stays unchanged, independent from the underlying hardware and provides therefore features, which the exploited physical host FPGA cannot provide. A special feature of the presented virtual FPGA amongst others is the dynamic reconfigurability which is for example not available with all off the shelf FPGAs. Furthermore the concept of FPGA virtualization enables the re-use of hardware blocks on other physical FPGA devices. This paper presents the hardware platform, describes the tool chain for the virtual FPGA and introduces with Core Fusion a novel technique that improves the utilization of the virtual FPGA.