A hardware-effective digital decimation filter implementation for 24-bit ΔΣ ADC

Abstract

A hardware-effective digital decimation filter implementation used in the 24-bit ΔΣ ADC for audio application is described in this paper. Composing of four comb filters and two half-band Finite Impulse Response (FIR) filters, the digital decimation filter uses multistage structure to relax the filter design. Since the multipliers are the most hardware consuming components in the digital filters, the coefficients of the FIR filters are coded by Canonical Signed Digit (CSD) which can make the filter multiplier-free. Meanwhile, time-multiplexing method is adopted in the filter to further reduce the hardware consumption. The proposed design is synthesized in 180nm CMOS process and occupies a die area of 1.44 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . This implementation is well suited for VLSI and can be applied to many other high resolution ΔΣ ADC.