A Hardware/Software Co-Design of MP3 Audio Decoder

Abstract

The Moving Picture Experts Group (MPEG) audio coding standard offers three levels of compression algorithms where the MPEG Layer III (MP3) has the best quality but with the most complexity. There are several complex coding techniques involved in MP3 audio decoding algorithm, therefore, it is difficult to make an efficient architecture design. This paper presents a hardware/software co-design method for the implementation of MP3 audio decoder, which meets the real-time requirement of MP3 standard. The software and hardware part of this decoder is partitioned into a pre-processing and a post-processing unit respectively. The pre-processing unit with a programmable parser processor is developed for the implementation of intensive decision making operations needed for audio bitstreams. The post-processing unit with a dedicated hardware of modified fast algorithm is designed for the regular and computation-intensive operations in MP3 audio decoding flow. The architecture achieves a high throughput with a reduced memory requirement and hardware complexity. With a two-level pipeline approach, it allows a high hardware utilization and is suitable to low power implementation. The proposed decoder system has been designed and implemented using VLSI cell-based approach. The die size is 3.5 × 4.45 mm2 with the maximum operation frequency of 20 MHz.