A hardware-oriented gold-washing adaptive vector quantizer and its VLSI architectures for image data compression

Abstract

The gold-washing (GW) mechanism is an efficient on-line codebook refining technique for adaptive vector quantization (AVQ). However, the mechanism is essentially not suitable for hardware implementation. We propose a hardware-oriented GW-AVQ scheme based on the least-recently-used (LRU) strategy for codevector selection and the block-data-interpolation (BDI) algorithm for vector generation. We also present the VLSI architectures for the key components of GW-AVQ, including a 2-D systolic array (SABVQ) and a 1-D linear array (LABVQ) for full-search VQ, a pipeline BDI encoder (PBDI-E) and decoder (PBDI-D), and the LRU strategy. The SABVQ architecture can perform in O(k) time with O(N+N/k) area and O(k) I/O complexity; the LABVQ architecture reaches O(N) time, O(k+1) area, and O(k) I/O complexity, where k and N are the codevector dimension and codebook size, respectively. The PBDI architecture reaches O(1) time, O(k) area, and O(1) I/O complexity. The LRU architecture can perform in O(1) time, O(N) area and O(1) I/O complexity. With VHDL implementation, the maximum computational capacity of SABVQ, LABVQ, five-stage PBDI-E, PBDI-D, and LRU are 45, 2.8, 1667, 2232, and 246 (10/sup 6/ samples/s), respectively. These results are good enough for most of the practical image compression systems.