A Hardware-in-the-Loop Platform for DC Protection

Abstract

Real-time (RT) simulation of power and energy conversion systems allows engineers to interface both simulation- and hardware-based controls using controller hardware-in-the-loop (CHiL) simulation of networks of power electronic converters (PECs) to de-risk highly developmental systems, such as next generation electrified transportation systems and dc microgrids. CHiL exploration and performance verification moves a design from technology readiness level (TRL) 3 to TRL 4 without incurring significant cost investments in developmental hardware platforms, which otherwise discourages such endeavors. An RT CHiL simulation platform suitable for explorations of protective equipment, protection schemes, and networked PEC dc and mixed dc-ac power distribution architectures must be capable of simulating common-mode behavior, various grounding schemes, and fault transients at sufficiently high resolution. This article demonstrates this capability using a latency-based linear multistep compound (LB-LMC) simulation method implemented in a commercially sustainable, adaptable, and expandable FPGA-based test and instrumentation platform. The proposed CHiL platform achieves RT power system simulations, including detailed switching commutations of networked PECs, with 50-ns resolution, and faithfully produces resonant and transient behaviors associated with line-to-ground (LG) and line-to-line (LL) faults and fault recovery in ungrounded PEC-based dc systems. This resolution in RT cannot be achieved with today's commercial off-the-shelf CHiL platforms. This article demonstrates the need for high-resolution RT simulation of LG and LL faults within dc systems, and demonstrates a CHiL approach that enables dc protection design explorations and protective control hardware testing while taking into account the realistic aspects that affect fault characteristics in PEC-based dc systems, such as cable current rating and length, cable and PEC parasitic LG capacitance, and PEC internal response to fault scenarios.