A hardware-implemented neural network for the analysis of handwritten numerals

Abstract

This study presents a specialized hardware-accelerated neural network tailored for the recognition of handwritten digits in 28x28 pixel grayscale images. Employing the perceptron model, our single-layer neural network is composed of 10 neurons, each handling inputs from all pixels to generate an output. The digit recognition is determined by the neuron with the highest output value. Implemented in synthesizable Verilog, the design complies with a constraint of 350 multipliers. To achieve this, this paper employs a combination of parallel processing and pipelining, breaking down the 785 multiplications needed for each digit into 8 stages, simultaneously processing 98 data points per clock cycle. In testbench evaluations, the final design exhibits impressive performance, successfully recognizing the majority of the provided images, and attaining a remarkable 99% accuracy rate, all with a minimal delay of just 115 clocks. This accomplishment is achieved using only 99 multipliers and 107 adders, showcasing the efficiency and effectiveness of our hardware-accelerated neural network for handwritten digit recognition.