A hardware implementation for full-search motion estimation of AVS with search center prediction

Abstract

This paper presents a full search motion estimation algorithm with search center prediction for AVS and the VLSI architecture to realize the algorithm. The proposed algorithm achieves comparable performance in coding efficiency with the anchor algorithm, whereas has low storage requirement, low required bandwidth and low complexity for the hardware implementation. The proposed architecture adopts 1-D PE arrays architecture and can perform variable block size motion estimation with 70 k logic gates and 24 kbits on-chip memory. The architecture achieves best tradeoff in terms of speed and hardware cost. The design can satisfy real-time encoding for AVS high definition application of 1280times720 picture size at 60 fps