Abstract
This paper presents a compact vector quantizer based on the self-organizing map (SOM), which can fulfill the data compression task for high-speed image sequence. In this vector quantizer, we solve the most severe computational demands in the codebook learning mode and the image encoding mode by a reconfigurable complete-binary-adder-tree (RCBAT), where the arithmetic units are thoroughly reused. In this way, the hardware efficiency of our proposed vector quantizer is greatly improved. In addition, by distributing the codebook into the multi-parallel processing sub-blocks, our design obtains a high compression speed successfully. Furthermore, a mechanism of partial vector-component storage (PVCS) is adopted to make the compression ratio adjustable. Finally, the proposed vector quantizer has been implemented on the field programmable gate array (FPGA). The experimental results indicate that it respectively achieves a compression speed of 500 frames/s and a million connections per second (MCPS) of 28,494 (compression ratio is 64) when working at 79.8 MHz. Besides, compared with the previous scheme, our proposed quantizer achieves a reduction of 8% in hardware usage and an increase of 33% in compression speed. This means the proposed quantizer is hardware-efficient and can be used for high-speed image compression.
Highlights
IntroductionHigh-speed image capture is one of the fundamental tasks for numerous industrial and scientific applications such as target tracking, optical scientific measurement, autonomous vehicles [1,2,3,4,5], etc
High-speed image capture is one of the fundamental tasks for numerous industrial and scientific applications such as target tracking, optical scientific measurement, autonomous vehicles [1,2,3,4,5], etc.Generally, in high-speed vision systems, the challenges of insufficient bandwidth and storage are increasingly severe and gradually become the bottlenecks
It consists of a shifter register with a depth of ‘7’, three registers with load signal, one ‘AND’ gate, one comparator, and an additional the distance calculation is fully conducted by the squared difference unit (SDU) and the reconfigurable complete-binary-adder-tree (RCBAT) circuit, and the operation of minimum distance search is mainly executed by a winner-takes-all (WTA) circuit
Summary
High-speed image capture is one of the fundamental tasks for numerous industrial and scientific applications such as target tracking, optical scientific measurement, autonomous vehicles [1,2,3,4,5], etc. Vector quantizer based on the SOM always shows plenty of excellent features such as inherent parallelism, regular topology, and relatively less well-defined arithmetic operations These features make the SOM-based vector quantizer quite favorable for hardware implementation and enable it to achieve high-speed image compression. In the previously proposed vector quantizers, many techniques were adopted to reduce the calculation complexity in the image encoding phase and realized lower resource usage. The previous designs normally required dedicated circuits to accomplish the codebook generation task Their entire hardware resource usages might be still high. Even though the authors in [13] presented a novel technique to accelerate the encoding process, the achievable speed of their quantizer was restricted by the intrinsic high-latency of their architecture.
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