A hardware based low temperature solution for VLSI testing using decompressor side masking

Abstract

The temperature of a block (a region in the chip) depends on both heat generation (caused by power consumption) and heat dissipation among neighbors. Power aware test solutions targeting low power consumption during testing, may not produce an acceptable thermal aware solution. In this paper, a hardware based solution using an AND-OR block between the decompressor and each scan chain, has been utilized to deactivate some scan chains during loading to reduce peak temperature during testing. The proposed schemes require negligible hardware overhead and do not require any special patterns. Experimental results of our proposed approach on ISCAS'89 and ITC'99 benchmark circuits show a good reduction in peak temperature.