A hardware algorithm for fast digit on-line logarithmic computation with exponential convergence rate

Abstract

In this research, a hardware algorithm for digit on-line logarithmic computation is proposed. This algorithm is based on a fast digit-parallel logarithmic algorithm that was proposed previously. The drawback of the previous algorithm is that the computation cannot be digit pipelined with other computations. Our new algorithm will generate the partial logarithmic result after only some input digits of the operand are available. Thus, the high throughput of the computing system can be attained with the use of digit pipelining in the design of the hardware architecture. Furthermore, the latency of the pipeline is short because the convergence rate of the algorithm is exponential. For example, when the word length of the operand is 24, the number of pipeline stages is only four. Base on our proposed digit on-line method, we have designed the architecture of a 24-bit logarithmic unit. The exhausted test of the 24-bit unit shows that our algorithm and error analysis are correct.