A half-adder (HA) and a full-adder (FA) combining single-electron transistors (SETs) with MOSFETs

Abstract

A half-adder (HA) and a full-adder (FA), using single-electron metal–oxide–semiconductor field-effect transistors (SE-MOSFET) hybrid circuits, are proposed. The proposed HA consists of three single-electron transistors (SETs), two enhancement-mode NMOSFETs and two depletion-mode NMOSFETs, and the proposed FA consists of four SETs, four enhancement-mode NMOSFETs, one enhancement-mode PMOSFET and three depletion-mode NMOSFETs. The total number of devices in the HA and the FA are 7 and 12, respectively. Compared with the conventional CMOS mirror FA with the 90 nm technology, the proposed FA can be constructed with 0.43 of devices and can operate with 5.6 of worst-case delay, 1/10.3 of average power consumption and 0.55 of power-delay product. The proposed HA and FA can be operated as a half-subtractor (HS) and a full-subtractor (FS) in the case when the levels of the control gates in the HA and the FA are suitably determined. The basic operations of the proposed HA, HS, FA and FS have been successfully confirmed through SPICE circuit simulation based on the physical device model of the SET.