A grid-based detailed routing algorithm for advanced 1D process

Abstract

End cutting 1D layout process is a promising candidate for sub-10nm process nodes. To be correctly manufactured, any pair of end cuts must be either merged/aligned or apart from each other with at least a minimum distance. This constraint adversely affects the manufacturability, especially when the end cuts have to be solely printed with the conventional lithography technology. To improve the manufacturability, recent works start to consider the constraint in early stages, such as physical design. In this paper, we propose a heuristic grid-based detailed routing algorithm for the end cutting 1D layout process. One important issue of the routing algorithm is how to represent the routing resources, especially for the end cuts. In the proposed algorithm, this issue is addressed by maintaining a directed routing graph. On the routing graph, new end cuts are initially located by a regular shortest path algorithm. Since the routing resources are correctly represented with the routing graph, the new end cuts are not in conflict with the existing end cuts. To further resolve the conflicts among the new end cuts, each segment of the wire is sequentially legalized. Experimental results indicate that compared with an intuitive two-stage method, the proposed algorithm can achieve higher solution quality with much less runtime.