Abstract
Coarse Grained Reconfigurable Arrays (CGRAs) have been more and more popular recently due to their high performance with low power consumption. An intelligent compiler is essential to execute applications on CGRAs effectively. However, automatically compilation for CGRAs still faces many challenges though many algorithms have been proposed. In this paper, we present an effective mapping algorithm which is targetable to a parameterized architecture template. The main contributions are an effective priority scheme, a satisfying backtracking algorithm and a fast control data flow graph (CDFG) splitting method. The experimental results demonstrate that our technique gains the performance very close to manual optimization.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
