A graph based synthesis procedure for linear analog function

Abstract

This paper presents a graph based synthesis procedure for reconfigurable linear analog function. A n-level weighted binary tree structure has been used to represent nth order linear network. Root of the binary tree has two children nodes with weights of first order lowpass filter (LPF) and first order highpass filter (HPF). Traversing through each possible path in the tree implements one filter type. The level 2 binary tree has been transformed to a hexagonal closed graph. This conversion has been done to map the proposed synthesis procedure into field programmable analog array (FPAA), which demonstrates the reusuability and programmability. First order LPF and HPF has been used as basic building blocks, whereas a hexagonal structure is denoted as a configurable analog block (CAB) of the FPAA. The hexagonal topology of the FPAA gives the versatile connectivity between two adjacent CABS of the FPAA. Performance has been verified through SPICE simulations.