A Graph-Based Method to Translate Relay Ladder Logic Diagrams

Abstract

The Relay Ladder Logic (RLL) graphic programming language is widely used to program Programmable Logic Controllers. A method to convert RLL diagrams into a set of Boolean expressions is presented. This method is based on the representation of each RLL network in terms of a directed graph. The original graph is reduced, in an iterative way, detecting and detaching parallel circuits by replacing groups of vertices by a single one. At the same time, each parallel circuit is independently translated. The logic expression for the reduced graph is then generated, and the final step is the recursive replacement of every reference to a parallel circuit by the sub-expression generated at reducing time.