A gm/ID Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators

Abstract

This article presents a methodology for sizing transistors of a multistage, multipath capacitor-less feed-forward compensated operational amplifiers employed in advanced CMOS process implementation of continuous-time bandpass $\Sigma \Delta $ -modulators. This article describes the methodology: on system level, dealing with the placement of poles and zeros; and on the circuit level, discussing issues related to biasing, frequency response and other important performance metrics of the basic diff-pair. Algorithms are provided to simplify mathematical aspects of the work. The validity and the limitations of the proposed methodology are further discussed from the single-pole system used to model the individual amplification stages of the multistage amplifier. The worthiness of the proposed methodology in sizing the transistors of complex amplifier structures, such as the capacitor-less multistage, multipath feed-forward-compensated amplifiers is demonstrated using two design examples. A third-order amplifier with a dc gain of 52.6 dB and that reaches a unity-gain frequency of above 14 GHz while consuming only 5.6 mA from a 1-V supply; and a fourth-order amplifier with dc gain of 73.5 dB that achieves a 25.7-dB gain at 1 GHz while consuming 4.8 mW are designed in 28-nm CMOS FDSOI.