A global interconnect design window for a three-dimensional system-on-a-chip

Abstract

A global interconnect design window for a three-dimensional system-on-a-chip (3D-SoC) is established by evaluating the constraints of 1) wiring area, 2) clock wiring bandwidth, and 3) crosstalk noise. This window elucidates the optimum 3D-SoC global interconnect parameters for minimum pitch, minimum aspect ratio, or maximum clock frequency. In comparison to a two-dimensional system-on-a-chip (2D-SoC), the design window is greatly expanded for a 3D-SoC, thus reducing the sensitivity to interconnect parameter variations. In addition, the maximum global clock frequency is revealed to increase as S/sup 1.5/, where S is the number of strata. For example, a 3D-SoC with two strata has a maximum global clock frequency 2.8 times that of a 2D-SoC. This increase in on-chip bandwidth, however, comes at the expense of I/O density, highlighting the necessity for new high-density-I/O packaging techniques.