A global approach to improve conditional hardware reuse in high-level synthesis

Abstract

The degree of conditional hardware reuse achieved after a high-level synthesis process depends on two factors: the number of mutually exclusive (mutex) operations pairs that an algorithm can detect and the description style used by the designer when specifying the system. In this paper, we propose a method that deals with both aspects. First, we propose a simple and homogeneous mechanism to analyze the input description and identify all the mutex operations pairs, independently of the conditional constructs (IF or CASE) used to specify the control flow of the system, and independently of the operators (logic or relational) needed to specify the conditions. Second, we provide a collection of formal transformations on the input description in order to overcome the non-intended design decisions (related to implicit hardware reuse) taken by the designer when writing the system description. Their application produces a specification of the same behavior that leads to improved implementations--in terms of the degree of conditional reuse that is achieved. Both facilities are possible thanks to the chosen internal representation mechanism, which is a mathematical model of the description, and to an underlying formal calculus that allows the description to be correctly manipulated. These ideas have been implemented in an algorithm that obtains better results than previous approaches.