Abstract
A Genetic Algorithm-Based Metaheuristic Approach for Test Cost Optimization of 3D SIC
Highlights
O VER the years, integrated circuit (IC) design has become important among researchers and industrial people, since it achieves high functionality and performance with less power consumption
During our experiment we observe that test cost gradually decreases with generation which indicates that the algorithm is robust and it will give us good quality as solution set is improving
design for testability (DFT) hardware and test time play a crucial role in increasing test cost of stacked integrated circuit (SIC)
Summary
O VER the years, integrated circuit (IC) design has become important among researchers and industrial people, since it achieves high functionality and performance with less power consumption. To achieve high functionality and performance IC design has become complex and interconnect has become a major source of circuit delay and power consumption. To reduce circuit delay and power consumption three dimensional integrated circuit (3D IC) (i.e. several layers are stacked together and some horizontal interconnect wires are replaced by vertical connection) is introduced. Exploring the use of the vertical dimension (3D) on both memory and logic [1], a wide range of applications of 3D IC on commercial products are seen in the market. A fieldprogrammable gate array routing switch using a 4-tier Monolithic 3D IC was designed by researchers from Stanford University in 2014 [5]. To improve the design of neuromorphic computing system in 3D IC, a
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