A General S-Domain Hierarchical Network Reduction Algorithm

Abstract

This paper presents an efficient method to reduce complexities of a linear network in s-domain. The new method works on circuit matrices directly and reduces the circuit complexities by eliminating subcircuits in a hierarchical way. The resulting admittances in the reduced networks are kept as rational functions of s with reduced order. Some theoretical results are characterized for the presence of common factors coming from the suppression of sub-circuits. A novel common factor removal (de-cancellation) strategy based on a graph-based hierarchical subcircuit reduction process is proposed. The resulting reduction algorithm is applicable to any linear circuits in s-domain. The stability of the reduced system is enforced by applying the Hurwitz polynomial approximation. The reduced systems can be used for fast s-domain analysis and for time domain waveform evaluation. Experimental results on both linear analog circuits and RLC circuits, and comparison with SPICE in s-domain analysis are also provided.