A general reconfiguration technique for fault tolerant processor architectures

Abstract

In this paper we present a new approach for fault tolerance in VLSI processor architectures. The reconfiguration technique is a general one in the sense that it can be applied to any arbitrary architecture with any number of spares each of which may be connected to an arbitrary number of processing elements. The technique is composed of two stages, local and global reconfiguration. In the local reconfiguration stage, faulty cells are maximally mapped onto adjacent spares. In the global stage, the shortest path from a faulty cell to a spare is found and the spare is propagated to the faulty site by the logical displacement of processing elements along that path.