Abstract
Using the processing power of multi-gigahertz general purpose processors (GPP) to perform radio functions can be a better and economical option to design a software defined radio (SDR) system. An efficient SDR system with multiple protocol support can be designed by identifying different blocks in the channel processing stream of different wireless protocols that can be mapped on GPP and field programmable gate arrays (FPGAs) processing platforms depending on throughput requirements of the corresponding protocol. This paper presents the ongoing research work in designing a novel architecture to prototype and develop efficient SDR systems using GPP as main digital signal processing (DSP) platform along with FPGAs to perform realtime signal processing tasks that can not be handled by GPPs. In this research project, a software defined radio is designed for the physical layer of WLAN standard IEEE 802.11a receiver. Different sub-systems of the channel processing stream of IEEE 802.11a OFDM receiver are mapped on GPP of a PC and a PCI board containing fast ADCs to receive the received analog signal from the RF front-end. The software radio architecture discussed in this paper is a scaled down version of the software radio that has to be developed as the research project for M. Engg. by research at NED University by the principal author.
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