A General Layout Pattern Clustering Using Geometric Matching Based Clip Relocation and Lower-Bound Aided Optimization

Abstract

With the continuous shrinking of feature size, detection of lithography hotspots has been raised as one of the major concerns in Design-for-Manufacturability (DFM) of semiconductor processing. Hotspot detection, along with other DFM measures, trades off turn-around time for the yield of IC manufacturing, thus a simplified but wide-range-covered pattern definition is a key essential to the problem. Layout pattern clustering methods, which group geometrically similar layout clips into clusters, have been vastly proposed to identify layout patterns efficiently. To minimize the clustering number for subsequent DFM processing, in this paper, we propose a geometric-matching-based clip relocation technique to increase the opportunity of pattern clustering. Particularly, we formulate the lower-bound of the clustering number as a maximum-clique problem, and we have also proved that the clustering problem can be solved by the result of the maximum-clique very efficiently. Compared with the experimental results of the state-of-the-art approaches on ICCAD 2016 Contest benchmarks, the proposed method can achieve the optimal solutions for all benchmarks with very competitive run-time. To evaluate the scalability, the ICCAD 2016 Contest benchmarks are extended and evaluated. And experimental results on the extended benchmarks demonstrate that our method can reduce the cluster number by 16.59% on average, while the run-time is 74.11% faster on large-scale benchmarks compared with previous works.