A Gb/s one-fourth-rate CMOS CDR circuit without external reference clock

Abstract

A 1-2.25 Gb/s clock and data recovery (CDR) circuit using 1/4th-rate digital quadricorrelator frequency detector and skew-calibrated multi-phase voltage-controlled oscillator is presented. With 1/4th-rate clock architecture, the coil-free oscillator can have lower operation frequency providing sufficient low-jitter operation. Moreover, it is inherent 1-to-4 DEMUX. The skew calibration scheme is applied to reduce phase offset in multi-phase clock generator. The CDR with frequency detector can have small loop bandwidth but wide pull-in range and can operate without the need for a local reference clock. This 1/4th-rate CDR is implemented in standard 0.18/spl mu/m CMOS technology. It has an active area of 0.7 mm/sup 2/ and consumes 100mW at 1.8V supply. The CDR has low jitter operation in a wide frequency range from 1-2.25 Gb/s. Measurement of bit-error rate is less than 10/sup -12/ for 2.25 Gb/s incoming data 2/sup 7/-1 PRBS, jitter peak-to-peak of 0.7 UI modulation at 10 MHz.