A Gate Driver Design for Medium Voltage Silicon Carbide Power Devices with High dv / dt

Abstract

The use of silicon carbide (SiC) devices in medium voltage (MV) applications has become a possibility due to the development of reliable MV SiC power devices. However, when SiC devices are used in these MV applications, they are exposed to a high voltage peak stress (of up to 15 kV across the primary and secondary side of the gate driver) and a very high $dv/dt$ (of up to 100 kV/μs across the isolation transformer). The gate driver design is very critical for proper functioning of the MV devices under the presence of such high dv/dt. This paper presents a design of an improved gate driver power isolation method, with a low coupling capacitance between the primary and the secondary side. The footprint of the isolation transformer is minimized to meet the clearance and insulation requirements. Comparisons have been drawn with an existing gate driver topology, on the basis of size of the gate driver, and common mode performances for different $dv/dt$ . Experimental results are provided to validate both the gate driver designs. The testing and analysis is carried out on a 10 kV SiC MOSFET developed and packaged by Wolfspeed. In addition, a brief discussion on the insulation standards for these kinds of applications is provided. The gate driver concept is aimed at providing a benchmark for building an efficient and reliable method to drive MV SiC devices.