A GA-based low-power Cache Partitioning algorithm for multi-programmed systems

Abstract

As the development of CMP, the size of on-chip cache increases and it consumes more and more power of the whole system. How to reduce the power consumption of cache has become a major concern nowadays. Cache partitioning techniques have been proposed to solve the cache pollution problem. The traditional cache partitioning mechanism, such as Utility-based Cache Partitioning (UCP) and IPC-based Cache Partitioning (IPC-CP), mainly focus on how to optimize the computing power. In this work, the cache partitioning technology considering power consumption is discussed. The lower-power oriented cache partitioning problem is presented as an optimization problem whose solution will place a set of cache ways in drowsy mode while keeping the performance degradation in a tolerated threshold. Since the problem is NP-Hard, a GA-based (genetic algorithm based) algorithm is proposed to find an approximate optimal solution. Our evaluation, on top of a two core CMP processor with a shared L2 cache, with 21 multi-programmed workloads, shows that the GA-based algorithm will always be more energy-efficient than traditional heuristic algorithm while the IPC won't decline much.