A Fundamental Modeling Approach for Nano-Grinding of Silicon Wafers

Abstract

The advantages of ductile regime grinding of silicon wafer such as smooth surface roughness (Ra < 10 nm) and minimum subsurface damage layer (< 10μm) have great impact on the production process of wafer. With ductile regime grinding, the subsequent processes such as etching and rough polishing processes can be minimized. To achieve ductile regime grinding, a fundamental concept is the application of grain depth of cut being less than the critical cut depth, dc, of the silicon wafer. However, dc is dependent on material properties, cutting conditions, and crystallographic orientation [1].The objective of this paper is to derive, and to investigate by experiment, the dc value for silicon wafer grinding. Following these key steps, the effects of dc on various major grinding parameters are studied.