Abstract
We describe a general purpose 40 MHz pipelined trigger processing board containing six look-up tables and the logic needed to programmably route the signals between them. A series of identical boards are connected in cascade in the NA48 CP-violation experiment at CERN, accept digital inputs generated from calorimeter signals and are used to perform the different computations necessary for the trigger reconstruction. The board architecture is designed to be flexible so that a single basic hardware design can perform all the different algorithms we require and so that the trigger algorithms can be adapted if needed. The computation latency of the combined network of eight boards is approximately 3 /spl mu/s. We present examples of some of the functions which have been implemented. We discuss the automatic reprogramming software which has been developed so that a new design can be implemented easily.
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