A Fully-Integrated High-Power Linear CMOS Power Amplifier With a Parallel-Series Combining Transformer

Abstract

In this paper, a linear CMOS power amplifier (PA) with high output power (34-dBm saturated output power) for high data-rate mobile applications is introduced. The PA incorporates a parallel combination of four differential PA cores to generate high output power with good efficiency and linearity. To implement an efficient on-chip power combiner in a small form-factor, we propose a parallel-series combining transformer (PSCT), which mitigates drawbacks and limitations of conventional power-combining transformers such as a series combining transformer (SCT) and a parallel combining transformer (PCT). Using the proposed PSCT, a two-stage class-AB PA is designed and fabricated in a 0.18-μm CMOS technology. The PA achieves a P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> of 31.5 dBm , a P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> of 34 dBm, and a P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">linear</sub> of 23.5 dBm with a peak PAE of 34.9% (peak drain efficiency of 41%) at the operating frequency of 2.4 GHz . A detailed analysis of the proposed PSCT is introduced along with comparisons to the conventional monolithic power-combining transformers. A design methodology of the integrated CMOS PA is also presented.