Abstract
Integrating a CMOS RF power amplifier (PA) into a single-chip transceiver is one of the most challenging works in implementing radio front-ends, which presents many advantages in handheld applications. Especially, low-power efficiency enhancement (LPEE) techniques, considering the probability distribution function of the practical wireless communication environments, extend the battery lifetime in handheld devices. Therefore, there are many studies for the LPEE in handheld CMOS PAs using transmission-line transformers (TLTs) with parallel amplifiers. Designing a series/parallel-combining transformer (SCT/PCT) is one of the key factors in the implementation of a dual-mode CMOS PA. However, the dual-mode performances of the PA must be optimized by using one output TLT structure. It is expected that there are difficulties in designing a highly efficient dual-mode PA. Therefore, this paper introduces a fully integrated dual-mode CMOS PA with a proposed output TLT with 2 control switches, which allows an LPEE with a back-off region of 10dB or more with a very low quiescent current.
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