Abstract
A fully-integrated dual-band Low Noise Amplifier (LNA), which can be used for IEEE 802.11 and Hiper LAN applications, was investigated in this paper. The proposed LAN was implemented entirely pm a single chip based on a standard 0.18 ?m 1P6M CMOS process. It draws 13 mA current from a 1.5-V voltage supply and achieves power gains of 17 and 10 dB, noise figure of 3.7 and 4.2 dB at 2.4 and 5.3 GHz respectively.
Highlights
COMS technology is becoming to a suitable technology for implementing wireless portable communication for terminals due to the fact that the gate lengths of MOS devices have been scaled down to submicron regime
The corresponding output noise is expressed as follows: Noise optimization: In CMOS Low Noise Amplifier (LNA) the MOS transistor usually operates in saturation region[6], a simplified equation for the drain current Ids when the transistor operates in saturation is[7]: in2,0,Rs =
The parasitic resistance of the on-chip inductors must be taken into account when doing noise optimization for a more accurate noise figure prediction
Summary
COMS technology is becoming to a suitable technology for implementing wireless portable communication for terminals due to the fact that the gate lengths of MOS devices have been scaled down to submicron regime. Its input impedance can be expressed as: one must introduce another zero point (corresponding to ω02) to the imaginary part, since the dual-band LAN has to operate in two different frequency bands The corresponding output noise is expressed as follows: Noise optimization: In CMOS LNAs the MOS transistor usually operates in saturation region[6], a simplified equation for the drain current Ids when the transistor operates in saturation is[7]: in2,0,Rs =.
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