Abstract
This paper presents a new design methodology and experimental results of a front end processor for 48/spl times/ speed CD-ROM drivers. The IC consists of a main signal processing block, a track error detecting block, a focus error detecting block, an automatic laser power control block, a center servo control block and other necessary servo signal generating blocks. The proposed front end processor for the 48/spl times/ speed CD-ROM driver systems was designed with a 0.8 um BICMOS technology process and the chip size is 3750 /spl mu/m/spl times/3750 /spl mu/m. Experimental results show that its performance meets or exceeds the requirements of the 48/spl times/ speed CD-ROM driver systems.
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