A front end electronic design with sliding ADC channels and X-Y decoder for a position sensitive scintillator block array

Abstract

This is an electronic design for a position sensitive detector system with a large array of crystal blocks (each block is composed of many crystals). The design goals are parts and space reduction. Each PMT has its fast amplifier and triggered integrator. Nine flash ADC, 3 adders, 2 EPROM and 10 program logic devices are used to determine the scintillation location for an array of 27 PMT and 784 crystals. The fast signals from one or more PMT clusters are summed. The fast summed signals are thresholded and sent to a GAL to determines the probable scintillation zone (several blocks) and to turn on the associated PMT integrators. After integration, the GAL also drives a set of ultra-fast analog switches to connect the flash ADC set (9 units) to the PMT integration channels in the scintillation zone. The 9 ADC output (integrated pulses with good photon statistics) are latched and compared. The comparator result determines which block in the probable zone is firing and the appropriate 4 ADC are selected and bused into a position decoder composed of 3 adders and a EPROM. The EPROM outputs the X-Y position along with the block-address. The circuit is pipelined and driven by a 250 MHz master clock. The maximum event-processing rate for the circuit and a random radiation source is 2/spl times/10/sup 6//sec (with 10:1 randomness allowance).