A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors

K Gavaskar,G Ravivarma,V Krithika Devi,M Megala,D Malathi,S Megaraj Begam

doi:10.1007/s11277-021-09407-x

Abstract

Digital Signal Processors play an unavoidable portion in modern-day communication. The Multiply Accumulate (MAC) is a crucial component of modern signal processors that performace is rely on speed, power, and area. In this paper, One such promising option is the Vedic multiplier based on the modified sum-product method is proposed. The MAC unit was built utilizing an outdated mathematical technique.The effectiveness of the vertical and transverse Vedic multiplication strategy that distinguishes itself in a true multiplier cycle. The architecture is designed for the proposed algorithm and coded in Verilog HDL. The design is synthesized for analyzing the area, power and delay in the Xilinx ISE environment. The proposed multiplier has 49.12% reduction in delay and a 42.51% reduction in power. When compared to the standard multiplier, it has a faster development practice and a lower calculation complexity.

Highlights

VLSI implies that Very Large Scale Integration, is the way of engendering an IC that is Integrated Circuit by which blending a great many semiconductors into a solo chip [1]
Multiply Accumulate (MAC) is an essential unit in the digital signal processors, to show the characters like speed, power as well as area
Comparing with existing multiplier the proposed 4x4 Vedic multiplier have 49.12% reduction in delay

Summary

Introduction

VLSI implies that Very Large Scale Integration, is the way of engendering an IC that is Integrated Circuit by which blending a great many semiconductors into a solo chip [1]. It is used in PC for microprocessor, digital camera and an electronic circuit which might consists of a CPU refers to Control processing Unit, ROM indicated as Read Only memory, RAM indicated as Random Access Memory, and other glue logic. Delay in VLSI is time trigger on any pin or net of interest and change in signal level of the same or other pin. While taking the static timing it evaluated the delays of whole paths

Methods

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Conclusion